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| july 2009 doc id 15084 rev 1 1/57 AN2836 application note l6225, l6226, l6227 dual full-bridge drivers 1 introduction modern motion control applicat ions need more flexibility that can be addressed only with specialized ic products. the l6225, l6226, l6227 are dual full-bridge driver ics specifically developed to drive a wide range of motors. these ics are one-chip, cost-effective solutions that include several unique circuit design features. these features allow the devices to be used in many applications including dc and stepper motor driving. the principal aim of this development project was to produce easy-to-use, fully-protected power ics. in addition several key functions such as protection circ uit and pwm current control drastically reduce the number of external components to meet requirements for many different applications. the l6225, l6226, l6227 are highly integrated, mixed-signal power ics that allow the user to easily design a control system for two-phase bipolar stepper motors, multiple dc motors and a wide range of inductive loads. figure 1 to figure 3 show the block diagrams of the l6225, l6226, l6227 . each ic integrates eight power dmos plus other added features for safe operation and flexibility. the l6227 also featur es a constant toff pwm current control technique (synchronous mode) for each of the two full bridges www.st.com
contents AN2836 2/57 doc id 15084 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 main differences betw een l6225, l6226, l6227 . . . . . . . . . . . . . . . . . . . 8 4 designing an application wi th l6225, l6226, l6227 . . . . . . . . . . . . . . 10 4.1 current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 voltage ratings and operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 choosing the bulk capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 sensing resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 charge pump external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 sharing the charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 reference voltage for pwm current control (l6227 only) . . . . . . . . . . . . 17 4.9 input logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 en pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 programmable off-time monostable (l6227 only) . . . . . . . . . . . . . . . . . . 20 4.12 off-time selection and minimum on-time (l6227 only) . . . . . . . . . . . . . . . 22 4.12.1 slow decay mode (l6227 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.13 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.14 adjusting the overcurrent detection trip point (l6226 only) . . . . . . . . . . . 27 4.15 paralleling two full bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.15.1 paralleling two full bridges to get a single full bridge . . . . . . . . . . . . . . . 29 4.15.2 paralleling the four half bridges to get a single half bridge . . . . . . . . . . 32 4.16 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.16.1 maximum output current vs. selectable devices . . . . . . . . . . . . . . . . . . 34 4.16.2 power dissipation and thermal analysis with practispin tm software . . 35 5 application example (l6227) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 appendix a demonstration boa rds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 a.1 practispin tm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AN2836 contents doc id 15084 rev 1 3/57 a.2 eval6225pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 a.2.1 important notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 a.3 eval6227pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 a.3.1 important notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 a.4 eval6226qr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 a.5 eval6227qr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 list of tables AN2836 4/57 doc id 15084 rev 1 list of tables table 1. rsense recommended values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2. application data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 3. motor data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 4. eval6225pd part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5. eval6227pd part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 6. eval6226qr part list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 7. eval6226qr part list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 AN2836 list of figures doc id 15084 rev 1 5/57 list of figures figure 1. l6225 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. l6226 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. l6227 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. supply voltage of high-side gate drivers versus supply voltage . . . . . . . . . . . . . . . . . . . . . 10 figure 5. currents and voltages during the deadtime at a phase change . . . . . . . . . . . . . . . . . . . . . 11 figure 6. voltage at the two outputs during the deadtime at a phase change . . . . . . . . . . . . . . . . . . 11 figure 7. typical application and layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. two situations that must be avoided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. sharing the charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. obtaining a variable voltage through a pwm output of a c . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. logic input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. ena and enb input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. pwm current control circuitry (l6227 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 15. pwm output current regulation waveforms (l6227 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. typical off-time vs. coff for several values of roff . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17. minimum on-time vs. coff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. slow decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19. pwm controller loses the current regulation due to minimum on-time (l6227 only) . . . . . 24 figure 20. pwm controller loses the current regulation due to minimum on-time (l6227 only) - detail24 figure 21. l6225 and l6227 overcurrent detection simplified circuitry . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22. l6226 overcurrent detection simplified circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23. overcurrent operation: timing 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 24. overcurrent operation: timing 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 25. typical disable time vs. c en for several values of r en . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 26. typical delay time vs. c en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 27. output current detection threshold versus r cl value (l6226 only) . . . . . . . . . . . . . . . . . . 28 figure 28. adjusting the ocd threshold through an external reference voltage (l6226 only). . . . . . . 28 figure 29. v s and sense pins maximum sourced current handling. . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 30. v s and sense pins maximum sinked current handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 31. l6225 parallel connection with lower overcurrent threshold . . . . . . . . . . . . . . . . . . . . . . . 30 figure 32. l6226 parallel connection with lower overcurrent threshold . . . . . . . . . . . . . . . . . . . . . . . 31 figure 33. l6227 parallel connection with lower overcurrent threshold . . . . . . . . . . . . . . . . . . . . . . . 31 figure 34. l6225 parallel connection for higher current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 35. l6226 parallel connection for higher current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 36. l6225 paralleling the four half bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 37. l6226 paralleling the four half bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 38. ic dissipated power versus output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 39. maximum output current vs. selectable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 40. power dissipation and thermal analysis with practispin tm software . . . . . . . . . . . . . . . . . 36 figure 41. application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 42. practispin tm pc software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 43. practispin tm st7 demonstration board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 44. eval6225pd board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 45. eval6225pd electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 46. eval6225pd component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 47. eval6225pd top layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 48. eval6225pd bottom laye r layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 list of figures AN2836 6/57 doc id 15084 rev 1 figure 49. eval6227pd board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 50. eval6227pd electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 51. eval6227pd component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 52. eval6227pd top layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 53. eval6227pd bottom laye r layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 54. eval6226qr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 55. eval6226qr comp onent placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 56. eval6226qr top layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 57. eval6226qr bottom layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 58. eval6226qr electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 59. eval6226qr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 60. eval6227qr comp onent placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 61. eval6227qr top layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 62. eval6227qr bottom layer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 63. eval6227qr electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 AN2836 references doc id 15084 rev 1 7/57 2 references 1. "a new fully integrated stepper motor driver ic", proceedings of pcim 2001, september 2001, intertech communication 2. "stepper motor driving" (an235) 3. "controlling voltage transients in fu ll bridge driver applications" (an280) 4. "a new high power ic surface mount package family" (an668) 5. "l6205, l6206, l6207 dual full bridge drivers" (an1762). main differences between l6225, l6226, l6227 AN2836 8/57 doc id 15084 rev 1 3 main differences between l6225, l6226, l6227 the l6225, l6226 and l6227 are dmos dual full-bridge ics. the l6225 (see figure 1 ) includes logic for cmos/ttl interface, a charge pump that provides auxiliary voltage to drive the hi gh-side dmos, non-dissipative overcurrent protection circuitry on the high-side dmos, with a fixed trip point set at 2.8 a (see section 4.13 ), overtemperature protection, undervoltage lockout for reliable startup. in addition, the l6226 (see figure 2 ) gives the possibility of adju sting the trip point of the overcurrent protection for each of the two full bridges (through two external resistors), and its internal open-drain mosfets (see section 4.13 ) are not internally connected to en pins but to separate ocd pins, allowing easier external diagnostics and overcurrent management. the l6227 (see figure 3 ) has an overcurrent protection function with a fixed trip point set at 2.8 a and internal open-drain mosfets connected to en pins, as the l6225, but it also integrates two pwm current controllers for each of the two full bridges (see section 4.11 ). figure 1. l6225 block diagram ! - v ' ! 4 % , / ' ) # / 6 % 2 # 5 2 2 % . 4 $ % 4 % # 4 ) / . / 6 % 2 # 5 2 2 % . 4 $ % 4 % # 4 ) / . ' ! 4 % , / ' ) # 6 # 0 6 " / / 4 % . ! ) . ! ) . ! % . " ) . " ) . " 6 " / / 4 6 6 6 3 ! 6 3 " / 5 4 ! / 5 4 ! / 5 4 " / 5 4 " 3 % . 3 % ! # ( ! 2 ' % 0 5 - 0 6 / , 4 ! ' % 2 % ' 5 , ! 4 / 2 4 ( % 2 - ! , 0 2 / 4 % # 4 ) / . 6 " / / 4 6 " / / 4 6 6 " 2 ) $ ' % ! " 2 ) $ ' % " 3 % . 3 % " / # $ ! / # $ " AN2836 main differences between l6225, l6226, l6227 doc id 15084 rev 1 9/57 figure 2. l6226 block diagram figure 3. l6227 block diagram ! - v $ ) . ! ' ! 4 % , / ' ) # / 6 % 2 # 5 2 2 % . 4 $ % 4 % # 4 ) / . / 6 % 2 # 5 2 2 % . 4 $ % 4 % # 4 ) / . ' ! 4 % , / ' ) # 6 # 0 6 " / / 4 % . ! ) . ! ) . ! % . " ) . " ) . " 6 " / / 4 6 6 6 3 ! 6 3 " / 5 4 ! / 5 4 ! / 5 4 " / 5 4 " 3 % . 3 % ! # ( ! 2 ' % 0 5 - 0 6 / , 4 ! ' % 2 % ' 5 , ! 4 / 2 4 ( % 2 - ! , 0 2 / 4 % # 4 ) / . 6 " / / 4 6 " / / 4 6 6 " 2 ) $ ' % ! " 2 ) $ ' % " 3 % . 3 % " 0 2 / ' # , " / # $ " / # $ ! 0 2 / ' # , ! / # $ ! / # $ " ! - v $ ) . ! ' ! 4 % , / ' ) # / # $ ! / # $ " / 6 % 2 # 5 2 2 % . 4 $ % 4 % # 4 ) / . / 6 % 2 # 5 2 2 % . 4 $ % 4 % # 4 ) / . ' ! 4 % , / ' ) # 6 # 0 6 " / / 4 % . ! ) . ! ) . ! % . " ) . " ) . " 6 2 % & ! 6 " / / 4 6 6 6 3 ! 6 3 " / 5 4 ! / 5 4 ! / 5 4 " / 5 4 " 3 % . 3 % ! # ( ! 2 ' % 0 5 - 0 6 / , 4 ! ' % 2 % ' 5 , ! 4 / 2 / . % 3 ( / 4 - / . / 3 4 ! " , % - ! 3 + ) . ' 4 ) - % 4 ( % 2 - ! , 0 2 / 4 % # 4 ) / . 6 " / / 4 6 " / / 4 6 6 " 2 ) $ ' % ! 3 % . 3 % # / - 0 ! 2 ! 4 / 2 " 2 ) $ ' % " 2 # ! 3 % . 3 % " 6 2 % & " 2 # " 0 7 - designing an application with l6225, l6226, l6227 AN2836 10/57 doc id 15084 rev 1 4 designing an application with l6225, l6226, l6227 4.1 current ratings with mosfet (dmos) devices, unlike bipolar transistors, current under short-circuit conditions is, at first approximation, limited by the r ds(on) of the dmos themselves and could reach very high values. l6225, l6226, l6227 out pins and the two v sa and v sb pins are rated for a maximum of 1.4 arms and 2.8 a peak (typical values), corresponding to a total (for the whole ic) 2.8 arms (5.6 a peak). these values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. in practical applications, though, maximum allowable current is less than these values, due to power dissipation limits (see section 4.16 ). the devices have a built-in overcurrent detection (ocd) that provides protection against short circuits between the outputs and between an output and ground (see section 4.13 ). 4.2 voltage ratings and operating range the l6225, l6226, l6227 require a single supply voltage (v s ), for the motor supply. internal voltage regulators provide the 5 v and 10 v required for the internal circuitry. the operating range for v s is 8 to 52 v. to prevent working from an undesirable low supply voltage an undervoltage lockout (uvlo) circuit shuts down the device when the supply voltage falls below 5.5 v. to resume normal operating conditions, v s must then exceed 6.3 v. the hysteresis is provided to avoid false intervention of the uvlo function during fast v s ringings. it should be noted, however, that r ds(on) of the dmos is a function of the v s supply voltage. actually, when v s is less than 10 v, r ds(on) is adversely affected, and this is particularly true for the high-side dmos that are driven from v boot supply. this supply is obtained through a charge pump from the internal 10 v supply, which tends to reduce its output voltage when v s goes below 10 v. figure 4 shows the supply voltage of the high-side gate drivers (v boot - v s ) versus the supply voltage (v s ). figure 4. supply voltage of high-side gate drivers versus supply voltage note that v s must be connected to both v sa and v sb since the bootstrap voltage (at v boot pin) is the same for the two h-bridges. the integrated dmos have a rated drain-source breakdown voltage of 60 v. however v s should be kept below 52 v, since in normal working conditions the dmos see a v ds voltage that exceeds v s supply. in particular, during a phase change (when each output of the same h-bridge switches from v s to gnd or vice versa, for example to reverse the current in the load) at the beginning of the deadtime (when all the dmos are off) the sense pin sees a negative spike due to a non-negligible parasitic ! - v 6 3 ; 6 = 6 " / / 4 6 3 ; 6 = AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 11/57 inductance of the pcb path from the pin to gnd. this spike is followed by a stable negative voltage due to the drop on r sense . one of the two out pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see figure 5 ). typical duration of this spike is 30 ns. at the same time, the other out pin of the same bridge sees a voltage above v s , due to the pcb inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. it turns out that the highest differential voltage can be observed between the two out pins of the same bridge, during the deadtime at a phase change, and this must always be kept below 60 v [ 3 ]. figure 5. currents and voltages during the deadtime at a phase change figure 6 shows the voltage waveforms at the two out pins referring to an application, with a peak output current of 1.4 a, v s = 52 v, r sense = 0.33 , t j = 25 c (approximately) and a good pcb layout. below ground spike amplitude is ?2.65 v for one output, the other out pin is at about 57 v. in these conditions, total differential voltage reaches almost 60 v, which is the absolute maximum rating for the dmos. keeping differential voltage between two output pins belonging to the same full bridge within rated values is a must that can be accomplished with proper selection of bulk capacitor value and equivalent series resistance (esr), according to current peaks and chopping style and adopting good layout practices to minimize pcb parasitic in ductances (see below) [ 3 ]. figure 6. voltage at the two outputs during the deadtime at a phase change ! - v 6 3 3 % . 3 % / 5 4 / 5 4 2 3 % . 3 % ) 2 3 % . 3 % ) 6 & $ i o d e 0 # " 0 a r a s i t i c ) n d u c t a n c e 0 # " 0 a r a s i t i c ) n d u c t a n c e " u l k # a p a c i t o r % q u i v a l e n t # i r c u i t % 3 2 % 3 , 2 3 % . 3 % 6 3 6 & $ i o d e $ a n g e r o u s ( i g h $ i f f e r e n t i a l 6 o l t a g e ! - v / u t / u t designing an application with l6225, l6226, l6227 AN2836 12/57 doc id 15084 rev 1 4.3 choosing the bulk capacitor since the bulk capacitor, placed between v s and gnd pins, is charged and discharged during the ic operation, its ac current capability must be grea ter than the rms value of the charge/discharge current. in case of pwm current regulation, the current flows from the capacitor to the ic during the on-time (t on ) and from the ic (implementing a fast decay current recirculation technique) or from the power supply (implementing a slow decay current recirculation technique) to the capacitor during the off-time (t off ). the rms value of the current flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty cycle and chopp ing style. it also depends on power supply characteristics. a power supply with poor high - frequency performances (or long, inductive connections to the ic) causes the bulk capaci tor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor. rms current in the capacitor, however, does not exceed the rms output current. bulk capacitor value ( c ) and the esr determine the amount of voltage ripple on the capacitor itself and on the ic. in slow decay, neglecting the deadtime and output current ripple, and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is: equation 1 , so the supply voltage ripple is: equation 2 where i out is the output current. with fast decay, instead, recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. this can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52 v). in fast decay the supply voltage ripple is about: equation 3 always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the deadtime. usually (if c > 100 f) the capacitance role is much less than the esr, then supply voltage ripple can be estimated as: equation 4 equation 5 v s i out ? esr t on c ---------- - + ?? ?? ? i out esr t on c ---------- - + ?? ?? ? i out 2esr ? t on t off + c -------------------------------- + ?? ?? ? i out esr ? in slow decay 2i ? out esr ? in fast decay AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 13/57 for example, if a maximum ripple of 500 mv is allowed and i out = 1 a, the capacitor esr should be lower than: equation 6 equation 7 actually, current sunk by the v sa and v sb pins of the device is subject to higher peaks due to the reverse recovery charge of the internal freewheeling diodes. the duration of these peaks is, though, very short, and can be filtered using a small value (100200 nf), good quality ceramic capacitors, connected as close as possible to the v sa , v sb and gnd pins of the ic. the bulk capacitor will be chosen with maximum operating volt age 25% greater than the maximum supply voltage, considering also power supply tolerances. for example, with a 48 v nominal power supply, with 5% tolerance, maximum voltage is 50.4 v, then operating voltage for the capacitor should be at least 63 v. 4.4 layout considerations working with devices that combine high power switches and control logic in the same ic, special attention has to be paid to the pcb layout. in extreme cases, power dmos commutation can induce noise that could cause improper operation in the logic section of the device. noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through gnd or supply connections. logic c onnections, especially high-impedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. with the l6225, l6226, l6227, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600 khz). the primary means to minimize conducted noise is to have a good gnd layout (see figure 7 ). figure 7. typical application and layout suggestions esr 0.5v 1a ------------ < 500m = in slow decay in fast decay esr 1 2 -- - 0.5v 1a ------------ ? < 250m = am01627v1 designing an application with l6225, l6226, l6227 AN2836 14/57 doc id 15084 rev 1 high-current gnd tracks (i.e. the tracks connect ed to the sensing resistors) must be connected directly to the negative terminal of the bulk capacitor. a good quality, high- frequency bypass capacitor is also required (typically a 100 nf200 nf ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. both bulk electrolytic and high-frequency bypass capacitors have to be connected with short tracks to v sa , v sb and gnd. on the l6225, l6226, l6227 gnd pins are the logic gnd, since only the quiescent current flows through them. logic gnd and power gnd should be connected together in a single point, the bulk capacitor, to keep noise in the power gnd from affecting logic gnd. specific care should be paid layouting the path from the sense pins through the sensing resistors to the negative terminal of the bulk capacitor (power ground). these tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on the sense and out pins (see section 4.2: voltage ratings and operating range ). for the same reason the capacitors on v sa , v sb and gnd should be very close to the gnd and supply pins. refer to section 4.5: sensing resistors for information on selecting the sense resistors. traces connected to v sa , v sb , sense a , sense b , and the four out pins must be designed with adequate width, since high currents are flowing through these traces, and layer c hanges should be avoided. should a layer change prove necessary, multiple and large via holes have to be used. a wide gnd copper area can be used to improve heat remova l, thus reducing thermal resistance. figure 8 shows two typical situations that must be avoided. an important consideration about the location of the bulk capacitors is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. the diode shown in figure 8 prevents the recirculation current from reaching the capacitors and results in a high voltage on the ic pins that can damage the device. having a switch or a power connection that can disconnect the capacitors from the ic, while there is still current in the motor, also results in a high-voltage transient since there is no capacitance to sink the recirculation current. figure 8. two situations that must be avoided ! - v ' . $ ' . $ ' . $ ' . $ 3 % . 3 % 3 % . 3 % ! " 6 3 ! 6 3 " 2 # # , , , 6 3 ? 6 $ / . { t c o n n e c t t h e l o g i c ' . $ h e r e 6 o l t a g e d r o p d u e t o c u r r e n t i n s e n s e p a t h c a n d i s t u r b l o g i c ' . $ $ / . { 4 p u t a d i o d e h e r e 2 e c i r c u l a t i n g c u r r e n t c a n n o t f l o w i n t o t h e b u l k c a p a c i t o r a n d c a u s e s a h i g h v o l t a g e s p i k e t h a t c a n d a m a g e t h e ) # AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 15/57 4.5 sensing resistors each motor winding current flows through the corresponding sensing resistor, causing a voltage drop that can be used by the logic (integrated in the l6227; an external logic can be used with l6225 and l6226) to control the peak value of the load current. two issues must be taken into account when choosing the r sense value: the sensing resistor dissipates energy and provides dangerous negative voltages on the sense pin during the current recirculation. for th is reason the resistance of this component should be kept low. the voltage drop across r sense is compared with a reference voltage (on v ref pin) by the internal comparator (l6227 only): the lower the r sense value, the higher the peak current error due to noise on the v ref pin and to the input offset of the current sense comparator. small values of r sense must be avoided. a good compromise is to calculate the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (i peak ), is about 0.5 v: r sense = 0.5 v / i peak . it should be clear that the sensing resistor must absolutely be non-inductive in order to avoid dangerous negative spikes on the sense pins. wire-wound resistors cannot be used here, while metallic film resi stors are recommended for their high peak current ca pability and low inductance. for the same reason the connections between the sense pins, c6, c7, v sa , v sb and gnd pins (see figure 7 ) must be made as short as possible (see also section 4.4: layout considerations ). the average power dissipated by the sensing resistor is: fast decay recirculation: p r i rms 2 r sense slow decay recirculation: p r i rms 2 r sense d where d is the duty cycle of the pwm current control and i rms is the rms value of the load current. nevertheless, the sensing resistor power rating should be chosen, taking into account the peak value of the dissipated power: equation 8 where i pk is the peak value of the load current. using multiple resistors in parallel helps to ob tain the required power rating with standard resistors, and reduces the inductance. the r sense tolerance reflects on the peak current error: 1% resistors should be preferred. ta bl e 1 shows the r sense recommended values (for a 0.5 v drop) and power ratings for typical examples of current peak values. p r i pk 2 r sense ? designing an application with l6225, l6226, l6227 AN2836 16/57 doc id 15084 rev 1 4.6 charge pump external components an internal oscillator, with its output at the cp pin, switches from gnd to 10 v with a typical frequency of 600 khz (see figure 9 ). figure 9. charge pump when the oscillator output is at ground, c 5 is charged by v s through d 2 . when it rises to 10, d 2 is reverse biased and the charge flows from c 5 to c 8 through d 1 , so the v boot pin, after a few cycles, reaches the maximum voltage of v s + 10 v - v d1 - v d2 , which supplies the high-side gate drivers. with a differential voltage between v s and v boot of about 9 v and both the bridges switching at 50 khz, the typical current drawn by the v boot pin is 1.85 ma. care must be taken in establishing the pcb layout of the c5, d1, d2 connections in order to minimize interferences with the rest of the circuit (see also section 4.4 ). recommended values for the charge pump circuitry are: d1, d2: 1n4148 c5: 10 nf 100 v ceramic c8: 220 nf 25 v ceramic due to the high charge pump frequency, fast diodes are required. connecting the cold side of the bulk capacitor (c8) to v s instead of gnd, the average current in the external diodes during operation is less than 10 ma. at ic power-up the current in the external diodes is less than 200 ma. the reverse voltage of the charge pump diodes is about 10 v in all table 1. r sense recommended values ipk r sense value [ ]r sense power rating [w] alternatives 0.25 2 0.125 0.5 1 0.25 10.5 0.5 2 x 1 , 0.25 w paralleled ! - v , , , 6 3 6 6 $ 6 3 6 $ f k ( z 6 3 ! 6 3 " 6 " / / 4 # 0 $ $ # # 2 $ 3 / . 6 6 6 2 $ 3 / . o h m o h m 4 o ( i g h 3 i d e ' a t e $ r i v e r s 6 f k ( z # h a r g e 0 u m p / s c i l l a t o r 6 3 6 6 $ 6 $ AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 17/57 conditions. the 1n4148 diodes withstand about 200 ma dc (1 a peak), and the maximum reverse voltage is 75 v, so they should fit for the majority of applications. 4.7 sharing the charge pump circuitry if more than one device is used in the application, it's possible to use the charge pump from one l6225, l6226 or l6227 to supply the v boot pins of several ics. the unused cp pins on the slave devices are left unconnected, as shown in figure 10 . a 100 nf capacitor (c8) should be connected to the v boot pin of each device. supply voltage pins (v s ) of the devices sharing the charge pump must be connected together. the higher the number of devices sharing the same charge pump, the lower the differential voltage available for the gate drive (v boot - v s ), causing a higher r ds(on) for the high-side dmos, thus higher dissipating power. better performance can also be obtained using a 33 nf capacitor for c5 and using schottky diodes (for example bat47 are recommended). sharing the same charge pump circuitry for more than 34 devices is not recommended, since it reduces the v boot voltage increasing the high-side mos on-resistance and thus power dissipation. figure 10. sharing the charge pump circuitry 4.8 reference voltage for pwm current control (l6227 only) the l6227 has two analog inputs, vref a and vref b , connected to the internal sense comparators, to control the peak value of the motor current through the integrated pwm circuitry. in typical applications these pins are connected together, in order to obtain the same current in the two motor windings. a fixed reference voltage can be easily obtained through a resistive divider from an available 5 v voltage rail (maybe the one supplying the c or the rest of the application) and gnd. a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a c (see figure 11 ). ! - v 6 3 ! 6 3 " 6 " / / 4 # 0 # n & 6 3 ! 6 3 " 6 " / / 4 # n & 4 o ( i g h 3 i d e ' a t e $ r i v e r s 4 o ( i g h 3 i d e ' a t e $ r i v e r s # 0 , , , , , , $ " ! 4 $ " ! 4 # n & 4 o o t h e r d e v i c e s designing an application with l6225, l6226, l6227 AN2836 18/57 doc id 15084 rev 1 figure 11. obtaining a variable voltage through a pwm output of a c assuming that the pwm output swings from 0 to 5 v, the resulting voltage is: equation 9 where d c is the duty cycle of the pwm output of the c. assuming that the c output impedance is lower than 1 k , with r lp = 56 k , r div = 15 k , c lp = 10 nf and a c pwm switching from 0 to 5 v at 100 khz, the low-pass filter time constant is about 0.12 ms and the remaining ripple on the v ref voltage is about 20 mv. using higher values for r lp , r div and c lp reduces the ripple, but the reference voltage takes more time to vary after changing the duty cycle of the c pwm, and too high values of r lp also increase the impedance of the v ref net at low frequencies, causing a poor noise immunity. as sensing resistor values are typically kept small, a small noise on the v ref input pins might cause a considerable error in the output current. it's then recommended to decouple these pins with ceramic capacitors of some te ns of nf, placed very close to the v ref and gnd pins. note that the v ref pins cannot be left unconnected, while, if connected to gnd, zero current is not guaranteed due to the voltage offset in the sense comparator. the best way to cut down the ic power consumption and clear the load current is to pull down the en pins. with very small reference voltage, pwm integrated circuitry can lose control of the current due to the minimum allowed duration of t on (see section 4.11 ). 4.9 input logic pins in1 a , in2 a , in1 b , in2 b are cmos/ttl compatible logic input pins. the input comparator has been configured with hysteresis to ensure the required noise immunity. typical values for turn-on and turn-off thresholds are v th,on = 1.8 v and v th,off = 1.3 v. as shown in figure 12 , these pins are esd-protected (2 kv hu man-body electro-static discharge), and can be directly connected to the logic outputs of a c. a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. all logic pins enforce a specific behavior and cannot be left unconnected. ! - v 5 / 3 & / 3 9 u h i * 1 ' 3 : 0 r x w s x w r i d ? & 5 ' , 9 v ref 5v d c r div ?? r lp r div + -------------------------------------------- - = AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 19/57 figure 12. logic input pins 4.10 en pins the en a , en b pins are, actually, bi-directional. as an input, with a comparator similar to the other logic input pins (ttl/cmos with hysteresis), they control the state of the power dmos. when each of the two pins is at a low logic level, all the power dmos of the corresponding h-bridge (a or b) are turned off. in l6225 and l6227 the en pins are also connected to the two corresponding open-drain out puts of the protection circuits that pull the pins to gnd if overcurrent in the corresponding h-bridge or overtemperature conditions exist. in l6226 the open-drain outputs are on separate pins, ocd a and ocd b , allowing easier external diagnostics and overcurrent management. for this reason, with l6225 and l6227 (and l6226 if en pins are connected to diag pins), en pins must be driven through a series resistor of 2.2 k minimum (for 5 v logic), to allow the voltage at the pin to be pulled below the turn-off threshold. a capacitor (c en in figure 13 ) connected between each en pin and gnd is also recommended, to reduce the rms value of the output current when overcurrent conditions persist (see section 4.13 ). the en pin must not be left unconnected. figure 13. en a and en b input pins ! - v 6 % 3 $ 0 r o t e c t i o n ! - v 6 0 5 3 ( 0 5 , , / 5 4 0 5 4 5 ( 1 & ( 1 ( 1 $ r u ( 1 % 2 & ' $ r u 2 & ' % 9 3 5 3 ( 0 5 , , / 5 4 0 5 4 5 ( 1 & ( 1 ( 1 $ r u ( 1 % ( 1 $ r u ( 1 % , , , designing an application with l6225, l6226, l6227 AN2836 20/57 doc id 15084 rev 1 4.11 programmable off-time monostable (l6227 only) the l6227 includes a constant off-time pwm current controller for each of the two bridges. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power mosfet transistors and ground, as shown in figure 14 . as the current in the load builds up, the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input (vref a or vref b ), the sense comparator triggers the monostable, switching the low-side mosfet off. the low-side mosfet remains off for the time set by the monostable and the motor current recirculates in the upper path. when the monostable times out, the bridge again turns on. since the internal deadtime, used to prevent cross conduction in the bridge, delays the turn- on of the power mosfet, the effective off-time is the sum of the monostable time plus the deadtime. figure 14. pwm current control circuitry (l6227 only) figure 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the rc pin voltage and the status of the bridge. immediately after the low-side power mosfet turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. the l6227 provides a 1 s blanking time t blank that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. ! - v ' 5 , 9 ( 5 6 ' ( $ ' 7 , 0 ( 6 4 5 ' 5 , 9 ( 5 6 ' ( $ ' 7 , 0 ( + + / / 2 8 7 $ r u % 6 ( 1 6 ( $ r u % 5 6 ( 1 6 ( 5 & $ r u % 5 2 ) ) & 2 ) ) 9 5 ( ) $ r u % , 2 8 7 2 8 7 $ r u % m v p $ % / $ 1 . ( 5 6 ( 1 6 ( & 2 0 3 $ 5 $ 7 2 5 & 2 0 3 $ 5 $ 7 2 5 2 8 7 3 8 7 0 2 1 2 6 7 $ % / ( 5 ( 6 ( 7 9 9 ) 5 2 0 7 + ( / 2 : 6 , ' ( * $ 7 ( ' 5 , 9 ( 5 6 / 2 $ ' $ r u % % / $ 1 . , 1 * 7 , 0 ( 0 2 1 2 6 7 $ % / ( 9 6 $ r u % 7 2 * $ 7 ( / 2 * , & AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 21/57 figure 15. pwm output current regulation waveforms (l6227 only) figure 16 shows the magnitude of the off time t off versus c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated deadtime with: 20 k r off 100 k 0.47 nf c off 100 nf t dt = 1 s (typical value) therefore: t off(min) = 6.6 s t off(max) = 6ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin rc a (or rc b ). the rise time t rcrise is only an issue if the ca pacitor is not completely charged before the next time the monostable is triggered. therefore, the on-time t on , which depends on motor and supply parameters, has to be longer than t rcrise in order to allow a good current regulation by the pwm stage. furthermore, the on-time t on cannot be shorter than the minimum on-time t on(min) . equation 10 equation 11 ! - v 2 ) ) % & ' ' $ w 2 1 w 2 ) ) % & 2 1 9 6 o r z ' h f d \ 6 o r z ' h f d \ m v w % / $ 1 . w 5 & 5 , 6 ( w 5 & 5 , 6 ( 6 < 1 & + 5 2 1 2 8 6 5 ( & 7 , ) , & $ 7 , 2 1 m v w % / $ 1 . 9 9 5 & 9 6 ( 1 6 ( 9 5 ( ) , 2 8 7 9 5 ( ) 5 6 ( 1 6 ( w 2 ) ) m v w ' 7 m v w ' 7 w 5 & ) $ / / w 5 & ) $ / / t on t on min () >1.5 s (typ. value) = t on t rcrise t dt ? > ? ? ? t rcrise 600 c off ? = designing an application with l6225, l6226, l6227 AN2836 22/57 doc id 15084 rev 1 4.12 off-time selection and mi nimum on-time (l6227 only) figure 17 also shows the lower limit for the on-time t on for having a good pwm current regulation capacity. it has to be said that t on is always longer than t on(min) because the device imposes this condition, but it can be shorter than t rcrise - t dt . in this last case the device continues to work, but the off-time t off is no longer constant. so, a small c off value gives more flexibility for the app lications (allows shorter on-time and, therefore, higher switching frequency), but the smaller the value for c off , the more influential the noise on the circuit performance. 4.12.1 slow deca y mode (l6227 only) figure 18 shows the operation of the bridge in the slow decay mode. at the start of the off time, the lower power mosfet is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the deadtime the upper power mosfet is operated in the synchronous rectification mode. when the monostable times out, the lower power mosfet is turned on again after a delay set by the deadtime to prevent cross conduction. figure 16. typical off-time vs. c off for several values of r off figure 17. minimum on-time vs. c off am016 3 6v1 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [nf] to f f [ us ] r = 20 k 3 7v1 coff [nf] 0.1 1 10 100 1 10 100 coff [nf] to n ( m in ) [ us ] AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 23/57 figure 18. slow decay mode output stage configurations in some conditions (short off-time, very low regulated current, high motor winding l / r) the system may need an on-time shorter than 1.5 s in which case the pwm current controller can lose the regulation. figure 19 shows the operation of the circuit in this condition. when the current first reaches the threshold, the bridge is turned off for a fixed time and the current decays. during the following on-time, the current increases above the threshold, but the bridge cannot be turned off until the minimum 1.5 s on-time expires. since the current increases more in each on-time than it decays during the off-time, it keeps growing during each cycle, with a steady state asymptotic value set by the duty cycle and load dc resistance. the resulting peak current is: equation 12 where d = t on / (t on + t off ) is the duty cycle and r load is the load dc resistance. ! - v " % - ) 4 . / ! ? s $ % ! $ 4 ) - % # 3 9 . # ( 2 / . / 5 3 2 % # 4 ) & ) # ! 4 ) / . $ ? s $ % ! $ 4 ) - % i pk v s d r load ----------------- - ? = designing an application with l6225, l6226, l6227 AN2836 24/57 doc id 15084 rev 1 4.13 overcurrent protection to implement an overcurrent protection, a dedicated overcurrent detection (ocd) circuitry (see figure 21 and 22 for a simplified schematic) senses the current in each high side. power dmos are actually made of thousands of individual identical cells, each carrying a fraction of the total flowing current. the current sensing element, connected in parallel to the power dmos, is made only of a few such cells, having a 1:n ratio compared to the power dmos. the total drain current is split between the output and the sense element according to the cell ratio. sensed current is, then, a small fraction of the output current and does not contribute significantly to power dissipation. figure 21. l6225 and l6227 overcurrent detection simplified circuitry figure 19. pwm controller loses the current regulation due to minimum on-time (l6227 only) figure 20. pwm controller loses the current regulation due to minimum on-time (l6227 only) - detail ! - v ! - v ! - v 2 9 ( 5 7 ( 0 3 ( 5 $ 7 8 5 ( , 5 ( ) , $ , $ q , $ q 3 2 : ( 5 6 ( 1 6 ( f h o o 3 2 : ( 5 6 ( 1 6 ( f h o o 3 2 : ( 5 ' 0 2 6 q f h o o v 3 2 : ( 5 ' 0 2 6 q f h o o v + , * + 6 , ' ( ' 0 2 6 v 2 ) 7 + ( % 5 , ' * ( $ 2 8 7 $ 2 8 7 $ 9 6 $ , $ , $ , $ q 2 & ' & 2 0 3 $ 5 $ 7 2 5 7 2 * $ 7 ( / 2 * , & , 1 7 ( 5 1 $ / 2 3 ( 1 ' 5 $ , 1 5 ' 6 2 1 7 7 < 3 & ( 1 5 ( 1 ( 1 $ 9 m & r u / 2 * , & , , AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 25/57 figure 22. l6226 overcurrent detection simplified circuitry this sensed current is compared to an internally-generated reference (adjustable through the external resistors r cla and r clb for l6226) to detect an overcurrent condition. an internal open-drain mosfet turns on when the sum of the currents in the bridges 1a and 2a or 1b and 2b reaches the threshold (2.8 a typical value for l6225 and l6227; adjustable through the external resistors r cla and r clb for l6226). in l6225 and l6227 the open drain is internally connected to the en pins. with l6226 the ocd pins should be connected to the en pins to allow the protection to function. to ensure an overcurrent protection, connect these pins to an external rc network (see figure 21 and 22 ). figure 23 and 24 show the device operating in overcurrent condition (short to ground). when an overcurrent is detected, the internal open-drain mosfet pulls the en pin to gnd, switching off all 4 power dmos of the bridge and allowing the current to decay. under a persistent overcurrent condition, like a short to ground or a short between two output pins, the external rc network on the en pin (see figure 21 and 22 ) reduces the rms value of the output current by imposing a fixed disable time after each overcurrent occurrence. the values of r en and c en are selected to ensure proper operation of the device under a short- circuit condition. when the current flowing through the high-side dmos reaches the ocd threshold (2.8 a typ. for l6225 and l6227, adjustable for l6226), after an internal propagation delay (t ocd(on) ) the open drain starts discharging c en . when the en pin voltage falls below the turn-off threshold (v th(off) ), all the power dmos turn off after the internal propagation delay (t d(off)en ). the current begins to decay as it circulates through the freewheeling diodes. since the dmos are off, there is no current flowing through them and no current to sense, so the ocd circuit, after a short delay (t ocd(off) ), switches the internal open - drain device off, and r en can charge c en . when the voltage at the en pin reaches the turn-on threshold (v th(on) ), after the t d(on)en delay, the dmos turns on and the current restarts. even if the maximum output current is very high, the external rc network provides a disable time (t disable ) to ensure a safe rms value (see figure 23 and 24 ). ! - v 2 9 ( 5 7 ( 0 3 ( 5 $ 7 8 5 ( , 5 ( ) , 5 ( ) , $ , $ q , $ q 3 2 : ( 5 6 ( 1 6 ( f h o o 3 2 : ( 5 6 ( 1 6 ( f h o o 3 2 : ( 5 ' 0 2 6 q f h o o v 3 2 : ( 5 ' 0 2 6 q f h o o v + , * + 6 , ' ( ' 0 2 6 v 2 ) 7 + ( % 5 , ' * ( $ 2 8 7 $ 2 8 7 $ 9 6 $ , $ , $ , $ q 2 & ' & 2 0 3 $ 5 $ 7 2 5 7 2 * $ 7 ( / 2 * , & , 1 7 ( 5 1 $ / 2 3 ( 1 ' 5 $ , 1 5 ' 6 2 1 7 7 < 3 & ( 1 $ 5 ( 1 $ 5 & / $ ( 1 $ 2 & ' $ 3 5 2 * & / $ 9 9 m & r u / 2 * , & , designing an application with l6225, l6226, l6227 AN2836 26/57 doc id 15084 rev 1 the maximum value reached by the current depends on its slew rate, thus on the state of the short-circuit, the supply voltage, and on the total intervention delay (t delay ). it can be noticed that after the first current peak, the maximum value reached by the output current becomes lower, because the capacitor on the en pins is discharged starting from a lower voltage, resulting in a shorter t delay . the following approximate relations estimate the disable time and the first ocd intervention delay after the short-circuit (worst case). the time the device remains disabled is: equation 13 where: equation 14 v en(low) is the minimum voltage reached by the en pin, and can be estimated by the relation: equation 15 the total intervention time is: equation 16 where figure 23. overcurrent operation: timing 1 figure 24. overcurrent operation: timing 2 ! - v ! - v en opdr off ocd en off d c r t t off th low en e v v ? + ? ? = ) ( ) ( ) ( ) ( en off d fall en on ocd delay t t t t ) ( ) ( ) ( + + = AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 27/57 equation 17 t ocd(off) , t ocd(on) , t d(on)en , t d(off)en , and r opdr are device intrinsic parameters, v dd is the pull-up voltage applied to r en . the external rc network, c en in particular, must be chosen in order to obtain a reasonably fast ocd intervention (short t delay ) and a safe disable time (long t disable ). figure 25 and 26 show both t disable and t delay as a function of c en : at least 100 s for t disable are recommended, keeping the delay time below 12 s at the same time. the internal open drain can also be turned on if the device experiences an overtemperature (ovt) condition. the ovt causes the device to shut down when the die temperature exceeds the ovt threshold (t j >165 c typ.). since the ovt is also connected directly to the gate drive circuits (see figure 1 to figure 3 ), all the power dmos shut down, even if the en pin voltage is still over v th(off) . when the junction temperature falls below the ovt turn-off threshold (150 c typ.), the open drain turns off, cen is recharged up to v th(on) and then the power dmos are turned back on. 4.14 adjusting the overcurrent de tection trip po int (l6226 only) the l6226 allows the user to set the overcurrent detection threshold separately for the two full bridges connecting two resistors (r cl ) to pins progcl a and progcl b . the ocd threshold (i sover ) follows the equations: i sover = 2.8 a 30% at -25 c < t j < 125 c if r cl = 0 (progcl connected to gnd) i sover = 10% at -25 c < t j < 125 c if 5 k < r cl < 40 k figure 27 shows the ocd threshold versus the r cl value in the range from 5 k to 40 k . ) off ( th dd en opdr ) fall ( en v v ln c r t ? ? = figure 25. typical disable time vs. c en for several values of r en figure 26. typical delay time vs. c en am01645v1 0 0 1 0 1 1 1 10 100 1 . 10 3 c en [n f ] t di s able [ s ] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k am01646v1 0 0 1 0 1 1 0.1 1 10 t delay [ s ] c en [n f ] c en [n f ] 11050 r cl ---------------- designing an application with l6225, l6226, l6227 AN2836 28/57 doc id 15084 rev 1 figure 27. output current detection threshold versus r cl value (l6226 only) the overcurrent detection threshold can also be adjusted through an external reference voltage, as shown in figure 28 . the external reference voltage source should be able to sink current (about 300 a maximum). moreover, if the supply voltage is provided to the l6226 before v ext , and its en pins are at a high logic level, the device starts working with minimum ocd threshold (actually the capacitor placed at the bottom of r cl allows a short startup time with a higher ocd threshold). v ext can also be obtained through a pwm output of a c, adding a series resistor to obtain a low-pass filter. the ocd threshold (i sover ) follows the equation: i sover = 10%, at -25 c < t j < 125 c if 0.25 a < i sover < 2.25 a figure 28. adjusting the ocd threshold through an external reference voltage (l6226 only) ! - v k k k k k k k k 5 # , > = , 3 / 6 % 2 ; ! = 9208.3 1.2v vext ? () r cl ------------------------------------------------------- ! - v 5 & / 3 5 2 * & / $ , 9 h [ w 9 AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 29/57 4.15 paralleling two full bridges 4.15.1 paralleling two full bridge s to get a single full bridge the outputs of l6225, l6226, l6227 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. it must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges (see figure 29 and 30 ). when the two halves of one full bridge (for example out1 a and out2 a ) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the powe r supply or sense pin. in addition, the overcurrent detection senses the sum of the current in the upper devices of each bridge (a or b), so connecting the two halves of one bridge in parallel does not increase the overcurrent detection threshold. figure 29. v s and sense pins maximum sourced current handling figure 30. v s and sense pins maximum sinked current handling ! - v 2 9 ( 5 & 8 5 5 ( 1 7 ' ( 7 ( & 7 , 2 1 9 6 $ 2 8 7 $ 6 ( 1 6 ( $ % 5 , ' * ( $ $ u p v $ s h d n 6 2 8 5 & ( ' , 2 8 7 , 2 8 7 , 6 8 3 3 / < $ u p v $ s n 6 2 8 5 & ( ' & x u u h q w 2 & ' 7 k u h v k r o g , 2 8 7 , 2 8 7 $ w \ s 2 8 7 $ 2 9 ( 5 & 8 5 5 ( 1 7 ' ( 7 ( & 7 , 2 1 9 6 % 2 8 7 % 6 ( 1 6 ( % % 5 , ' * ( % $ u p v $ s h d n 6 2 8 5 & ( ' , 2 8 7 , 2 8 7 , 6 8 3 3 / < $ u p v $ s n 6 2 8 5 & ( ' & x u u h q w 2 & ' 7 k u h v k r o g , 2 8 7 , 2 8 7 $ w \ s 2 8 7 % ! - v 6 , 1 . ( ' , 2 8 7 , 2 8 7 , 6 ( 1 6 ( $ u p v $ s n 9 6 $ 2 8 7 $ 6 ( 1 6 ( $ % 5 , ' * ( $ $ u p v $ s h d n 2 8 7 $ 6 , 1 . ( ' , 2 8 7 , 2 8 7 , 6 ( 1 6 ( $ u p v $ s n 9 6 % 2 8 7 % 6 ( 1 6 ( % % 5 , ' * ( % $ u p v $ s h d n 2 8 7 % designing an application with l6225, l6226, l6227 AN2836 30/57 doc id 15084 rev 1 this configuration has to be used when two separate loads are driven, since the ics have only two enable inputs, one for the full bridge a and the other for the bridge b. in this case pulling to gnd one of the two enable pins disables only one load (see figure 31 to 33 ). this configuration can also be used if a 2.8 a ocd threshold is desired (instead of 5.6 a). half-bridge 1 and the half-bridge 2 of the bridge a are connected in parallel and the same is done for the bridge b as shown in figure 31 to 33 . in this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device is reduced, but the pe ak current rating is not increased. using this configuration with l6226, two separate resistors connected to pins progcl a and progcl b must be used. with l6227, two separate rc networks should be used on the rc pins. when two different loads are driven (see figure 33 ) by the two equivalent half bridges, two separate sensing resistors are needed, while if the two equivalent half bridges drive two separate loads, they must be connected from the out pins to v s (see figure 33 ) to make the pwm current control work properly. in this configuration, the resulting bridge has the following characteristics (typical values). equivalent device: full bridge r ds(on) hs + r ds(on) ls 0.73 typ. value at t j = 25c 1.4 a max rms load current 2.8 a ocd threshold figure 31. l6225 parallel connection with lower overcurrent threshold ! - v & 3 & % 2 2 7 5 3 ' ' & 2 8 7 $ 2 8 7 $ * 1 ' * 1 ' * 1 ' * 1 ' 2 8 7 % 2 8 7 % 9 6 $ 3 2 : ( 5 * 5 2 8 1 ' 6 , * 1 $ / * 5 2 8 1 ' 9 6 9 ' & 9 6 % 9 & 3 9 % 2 2 7 & 6 ( 1 6 ( $ 6 ( 1 6 ( % , 1 $ , 1 % , 1 $ , 1 $ , 1 % , 1 % ( 1 % ( 1 $ & ( 1 5 ( 1 ( 1 , / 2 $ ' / 2 $ ' AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 31/57 figure 32. l6226 parallel connection with lower overcurrent threshold figure 33. l6227 parallel connection with lower overcurrent threshold for some applications the recommended configuration is half bridge 1 of bridge a paralleled with the half-bridge 1 of the bridge b, and the same for the half-bridges 2 as shown in figure 34 and 35 . figure 34. l6225 parallel connection for higher current ! - v & 3 & % 2 2 7 5 3 ' ' & 2 8 7 $ 2 & ' $ 2 & ' % 2 8 7 $ * 1 ' * 1 ' * 1 ' * 1 ' 3 5 2 * & / $ 2 8 7 % 2 8 7 % 9 6 $ 3 2 : ( 5 * 5 2 8 1 ' 6 , * 1 $ / * 5 2 8 1 ' 9 6 9 ' & 9 6 % 9 & 3 9 % 2 2 7 & 6 ( 1 6 ( $ , 1 $ , 1 $ , 1 $ ( 1 $ ( 1 % & ( 1 5 ( 1 ( 1 , 1 % , 1 % , 1 % 6 ( 1 6 ( % 5 & / $ 3 5 2 * & / % 5 & / % , / 2 $ ' / 2 $ ' ! - v & 3 & % 2 2 7 5 3 ' ' & 2 8 7 $ 2 8 7 $ * 1 ' * 1 ' * 1 ' * 1 ' 2 8 7 % 2 8 7 % 9 6 $ 3 2 : ( 5 * 5 2 8 1 ' 6 , * 1 $ / * 5 2 8 1 ' 9 6 9 ' & 9 6 % 9 & 3 9 % 2 2 7 & 6 ( 1 6 ( $ 6 ( 1 6 ( % , 1 $ , 1 % , 1 $ , 1 $ , 1 % , 1 % ( 1 % ( 1 $ & ( 1 5 ( 1 ( 1 , 9 5 ( ) % 9 5 ( ) $ 5 & % 5 % & % 5 & $ 5 $ & $ 9 5 ( ) 9 5 6 ( 1 6 ( / 2 $ ' 5 6 ( 1 6 ( / 2 $ ' 9 6 9 6 ! - v 2 8 7 $ 2 8 7 % * 1 ' * 1 ' * 1 ' * 1 ' 2 8 7 % 2 8 7 $ 9 6 $ 3 2 : ( 5 * 5 2 8 1 ' 6 , * 1 $ / * 5 2 8 1 ' 9 6 9 ' & 9 6 % 9 & 3 9 % 2 2 7 & 6 ( 1 6 ( $ ( 1 % 6 ( 1 6 ( % / 2 $ ' ( 1 $ & ( 1 5 ( 1 ( 1 , 1 , 1 $ , 1 % , 1 % , 1 $ , 1 & 3 & % 2 2 7 5 3 ' ' & , designing an application with l6225, l6226, l6227 AN2836 32/57 doc id 15084 rev 1 figure 35. l6226 parallel connection for higher current this configuration cannot be used with l6227, because of its internal pwm current controllers that work separately for bridge a and bridge b. using this configuration with the l6227 may damage the device. in this configuration the resulting bridge has the following characteristics (typical values): equivalent device: full bridge r ds(on) hs + r ds(on) ls 0.73 typ. value at t j = 25 c 2.8 a max rms load current 5.6 a ocd threshold it should be noted that using two separate loads for the two equivalent half bridges the maximum current cannot be sourced or sinked simultaneously by the two equivalent half bridges (for example to drive two separate loads), due to the 2.8 a maximum current limit for the v s and sense pins (see figure 29 and 30 ). when a single load is driven (see figure 34 and 35 ), the r cla and r clb resistors connected to the progcl pins of l6226 should have the same value. 4.15.2 paralleling the four half bridges to get a single half bridge it is also possible to parallel the four half bridges to obtain a simple half bridge as shown in figure 36 and 37 . this configuration cannot be used with l6227, because of its internal pwm current controllers that work separately for bridge a and bridge b. using this configuration with the l6227 may damage the device. the resulting half bridge has the following characteristics (typical values): equivalent device: half bridge r ds(on) hs + r ds(on) ls 0.36 typ. value at t j = 25 c 2.8 a max rms load current 5.6 a ocd threshold when the l6226 is used in this configuration, r cla and r clb resistors connected to progcl pins must have the same value. ! - v & 3 & % 2 2 7 5 3 ' ' & 2 8 7 $ / 2 $ ' 2 & ' $ 2 & ' % 2 8 7 $ * 1 ' * 1 ' * 1 ' * 1 ' 3 5 2 * & / $ 2 8 7 % 2 8 7 % 9 6 $ 3 2 : ( 5 * 5 2 8 1 ' 6 , * 1 $ / * 5 2 8 1 ' 9 6 9 ' & 9 6 % 9 & 3 9 % 2 2 7 & 6 ( 1 6 ( $ , 1 , 1 $ , 1 % ( 1 $ ( 1 % 5 ( 1 ( , 1 % , 1 $ , 1 6 ( 1 6 ( % 5 & / $ & ( 1 3 5 2 * & / % 5 & / % , AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 33/57 figure 36. l6225 paralleling the four half bridges 4.16 power management even when operating at current levels well below the maximum ratings of the device, the operating junction temperature must be kept below 125 c. figure 38 shows the ic dissipated power versus the rms load current, in the case of: a single ic driving two loads (for instance 2 dc motors or a two-phase stepper motor) or a single ic, with two fu ll bridges paralleled (see section 4.15: paralleling two full bridges ) driving one load (for instance 1 dc motor or one phase of a two-phase stepper motor) and assuming the supply voltage is 24 v. figure 37. l6226 paralleling the four half bridges ! - v & 3 & % 2 2 7 5 3 ' ' & 2 8 7 $ 2 8 7 % * 1 ' * 1 ' * 1 ' * 1 ' 2 8 7 % 2 8 7 $ 9 6 $ 3 2 : ( 5 * 5 2 8 1 ' 6 , * 1 $ / * 5 2 8 1 ' 9 6 9 ' & 9 6 % 9 & 3 9 % 2 2 7 & 6 ( 1 6 ( $ ( 1 % 6 ( 1 6 ( % ( 1 $ & ( 1 5 ( 1 ( 1 , 1 $ , 1 % , 1 % , 1 $ / 2 $ ' , 1 , ! - v designing an application with l6225, l6226, l6227 AN2836 34/57 doc id 15084 rev 1 4.16.1 maximum output curre nt vs. selectable devices figure 39 shows a comparison of performance between different devices of the powerspin tm family, for different packages and in a parallel configuration, with the following assumptions: each equivalent full bridge drives a load supply voltage: 24 v; switching frequency: 30 khz t amb = 25 c, t j = 125 c maximum r ds(on) (taking into account process spread) has been considered, at 125 c maximum quiescent current i q (taking into account process spread) has been considered pcb is an fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m) for so and powerdip packages (d, n suffixes) pcb is an fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer for the powerso package (pd suffix) for each device configuration (on the x-ax is) the y-axis shows the maximum output (load) current 2 x ?device? means that the two loads are driven by two equivalent full bridges obtained by paralleling two full bridges for each of the two ics used. the current reported in figure 39 is the maximum output current of an equivalent full bridge (a paralleled ic). figure 38. ic dissipated power versus output current ! - v AN2836 designing an application with l6225, l6226, l6227 doc id 15084 rev 1 35/57 figure 39. maximum output current vs. selectable devices 4.16.2 power dissipation and ther mal analysis with practispin tm software the practispin tm software includes a power dissipation and thermal analysis section that helps in calculating the ic power dissipation and estimating its junction temperature, through a simulation. this section is intended to help to give a fast evaluation of the device, package and dissipating copper area required by the user?s application, and to be a good starting point for designing an application (from the power dissipation and thermal point of view). software results, especially thermal results, need to be confirmed on the bench. the input data for simulation are divided in three sections: a) application data: to select the motor characteristics and its configuration, the driving parameters and the analysis type (steady state, single pulse or repeated pulse analysis). b) device data: to choose the device part number and to edit some available ic parameters. c) pcb data: to select the package, the pcb dissipating charcteristics and ambient temperature. the output data include the waveforms of temperature and current profile, the estimated ic power dissipation and junction temperature. for more details on the formulas used in the software , please refer to the "help" menu of ?power dissipation and thermal analysis?. ! - v / ; ' / ; 1 / ; 3 ' / ; ' / ; 1 / ; 3 ' [ / ; ' [ / ; 1 [ / ; 3 ' [ / ; ' [ / ; 1 [ / ; 3 ' , o a d c u r r e n t ; ! = designing an application with l6225, l6226, l6227 AN2836 36/57 doc id 15084 rev 1 figure 40. power dissipation and thermal analysis with practispin tm software am01660v1 AN2836 application example (l6227) doc id 15084 rev 1 37/57 5 application example (l6227) the bulk capacitor needs to withstand at least 24 v + 5% + 25% ? 32 v. a 50 v capacitor is used. allowing a voltage ripple of 200 mv, the capacitor esr should be lower than 200 mv / 0.5 a = 400 m . the ac current capab ility should be about 0.5 a. providing a reference voltage of 0.5 v, a sensing resistor of 1 is needed. loading the input data on the power dissipation and thermal analysis section, the resulting switching frequency is 11.9 khz. the on-time is t on = (1 / f sw ) - t off ? 70 s, which is far from the minimum allowed (1.5 s), so slow decay can be used. the duty cycle is d ? 78%. the sense resistors? power rating is about p r ? i rms 2 r sense d ? 0.25 w. a 1 - 0.25 w - 1% resistor is used. the charge pump uses recommended components (1n4148 diodes and ceramic capacitors). r = 18 k , c = 1.2 nf are connected to the rc pins, obtaining t off ? 16 s. on the en pins 5.6 nf capacitors have been placed, and the pins are driven by the c through 100 k resistors. with these values, in case of short-circuit between two out pins or an out pin and gnd, the powerdmos turns off after about 1 s, and t disable ? 240 s. table 2. application data application data value rotation speed 300 rpm (f ck =1 khz) winding peak current 0.5 a maximum ripple 50 ma supply voltage 24 v 5 % sequence wave mode off time 15 s table 3. motor data motor data value winding resistance 6.6 winding inductance 7.9 mh step angle 1.8 / step maximum bemf at 300 rpm 15 v application example (l6227) AN2836 38/57 doc id 15084 rev 1 figure 41. application example with wave drive selected, the dissipating power is about 0.8 w. if the ambient temperature is about 50 c, with 4 cm 2 of copper area on the pcb and a so24 package, the estimated junction temperature is about 94c. using more copper area or a powerdip package reduces the junction temperature. am01661v1 AN2836 demonstration boards doc id 15084 rev 1 39/57 appendix a demonstration boards a.1 practispin tm practispin tm is an evaluation and demonstration system that can be used with the powerspin tm family of devices. a graphical user interface (gui) program (see figure 42 ) runs on an ibm-pc under windows and communicates with a common st7-based interface board (see figure 43 ) through the rs232 serial port. the st7 interface board is connected to a device-specific board (target board) via a standard 34-pin ribbon cable interface. depending on the target device, the practispin tm can drive a stepper motor, 1 or 2 dc motors or a brushless dc (bldc) motor, setting significant parameters such as speed, current, voltage, direction, acceleration and deceleration rates from a user friendly graphic interface, and programming a sequence of movements. the software also allows evaluating the power dissipated by the selected device and, for a given package and dissipating copper area on the pcb, estimates the junction temperature of the device. figure 42. practispin tm pc software am01662v1 demonstration boards AN2836 40/57 doc id 15084 rev 1 figure 43. practispin tm st7 demonstration board a.2 eval6225pd a demonstration board has been produced to help the evaluation of the device in a powerso package. it implements a typical application with several added components. figure 45 shows the electrical schematic of the board. ta bl e 1 gives the part list. ! - v table 4. eval6225pd part list part reference value description cn1, cn2, cn3, cn4 2-pole connector cn5 34-pole connector c1 220 nf/100 v ceramic or polyester capacitor c2 220 nf/100 v ceramic or polyester capacitor c3 100 f/63 v capacitor c4 10 nf/100 v ceramic capacitor c5 10 f/16 v capacitor c6, c7 5.6 nf capacitor c11 100 nf capacitor c8, c10 470 pf capacitor c9, c12 68 nf capacitor c13 2.2 nf capacitor d1 bat46sw diode d3 bzx79c5v1 5.1 v zener diode jp1 3-pole jumper r1 0 resistor r2 700 0.6 resistor r13 10 k resistor r3, r4, r5, r6 100 k resistor AN2836 demonstration boards doc id 15084 rev 1 41/57 the demonstration board provides external connectors for the supply voltage, an external 5v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external c board or the practispin tm tool. the board also accommodates the l6506 pwm current controller. r23 sets the pwm operating frequency. if the l6506 does not need to be used, simply connect the two v ref inputs to a voltage high enough to keep current control inactive. the practispin tm tool is composed of a graphic interface software running on a pc that connects with the hardware based on the st7 c, which contains upgradable firmware. this tool allows a fast and easy evaluation of the powerspin tm family of devices, allowing to drive dc, bldc and stepper motors, depending on the target device. the practispin connected to the eval6225pd can drive dc motors and inductive loads, allowing output voltage and current settings. the pc software also provides a power dissipa tion and thermal analysis section, intended to help give a fast evaluation of the device, package and dissipating copper area required by the user?s application, and to be a good starting point for designing an application (from the power dissipation and thermal point of view). running the demonstration board in standalone mode, instead, r17 and r21 set the reference voltage separately for the two bridges, while r16, c9 and r20, c12 are low-pass filters which provide an external reference voltage by a pwm output of a c (see also the microstepping section in the an2839). using external v ref inputs, r15, r1 7, r19, r21 can be disconnected through jp4 and jp5, unless the practispin tm st7 demonstration board is used. this board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see practispin tm documentation). closing jp2 and jp3 is recommended for safe overcurrent protection. the 5 v voltage for logic inputs and for references (v refa and v refb ) is obtained from r2, d3. depending on the supply voltage, the value of resistor r2 should be changed in order to ensure a correct biasing of d3. the jumper jp1 allows choosing the 5 v voltage from the internal zener diode network or pin 11 of cn5 (for example an external c board can provide 5 v to the demonstration board). also a cn2 connector can be used to provide an external 5 v voltage to the board (in that case r2, d3 should be disconnected). cn2, or pin 1 of cn5, can also be used to provide a 5 v voltage to external circuits (as, for example, the practispin tm st7 board). in r7, r9, r10, r12 1 0.4 resistor r18, r14 1 k resistor r15, r19 20 k resistor r16, r20 2.2 k resistor r17, r21 5 k tr i m m e r r22 12 k resistor r23 50 k tr i m m e r u1 l6225pd l6225pd u2 l6506d l6506d jp2, jp3, jp4, jp5, jp6 2-pole jumper table 4. eval6225pd part list (continued) part reference value description demonstration boards AN2836 42/57 doc id 15084 rev 1 this case the current that can be drawn from the board depends on the supply voltage and on the value of r2. figure 46 to 48 show the placement of the components and the two-layer layout of the l6225pd demonstration board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device. figure 44. eval6225pd board a.2.1 important notes jp1: closed in int position for use with practispin tm st7 board r17, r21: set the maximum current obtainable through practispin (see practispin tm documentation) r2 : recommended to be changed to adequate value (depending on supply voltage) to obtain 5 v across d3 jp2, jp3 : closed for safe overcurrent protection jp4, jp5 : closed for use with practispin tm st7 board jp6: open for use with practispin tm st7 board. ! - v 2 * 0 * 0 * 0 * 0 2 2 * 0 2 AN2836 demonstration boards doc id 15084 rev 1 43/57 figure 45. eval6225pd electrical schematic ! - v , 1 , 1 , 1 , 1 b b b b 9 5 ( ) b $ 9 5 ( ) b % 6 ( 1 6 ( b % 6 ( 1 6 ( b $ / , 0 , 7 b % b / , 0 , 7 b $ b b ( 1 % b , 1 ( 1 $ 9 5 ( ) $ 9 5 ( ) % , 1 / , 0 , 7 b % ( 1 % , 1 , 1 / , 0 , 7 b $ ( 1 $ 6 ( 1 6 ( b $ 6 ( 1 6 ( b % 3 x o o 8 s 3 x o o 8 s 3 x o o 8 s 9 & & 5 ( ) 3 x o o 8 s 3 x o o 8 s 3 x o o 8 s 9 3 x o o 8 s 9 * 1 ' 9 l q 6 ( 1 6 ( $ 6 ( 1 6 ( % 7 1 , ) ( 5 b & ' $ , 1 7 2 & 0 3 $ 3 7 , 1 $ 3 7 , 1 $ 3 7 2 8 7 3 % 2 & 0 3 % , & $ 3 % 3 7 , 1 % 3 7 2 8 7 $ 3 , 1 7 , 1 7 7 , 1 % 3 7 2 8 7 % 3 & : l q w h [ w & : w x v w x v ' ' & 1 & 1 5 5 5 5 5 5 ' ' & 1 & 1 5 5 2 8 7 % 2 8 7 $ , 1 $ , 1 $ 6 ( 1 6 ( $ 2 8 7 $ * 1 ' * 1 ' 6 ( 1 6 ( % , 1 % , 1 % ( 1 % 9 % 2 2 7 2 8 7 % 9 6 % * 1 ' * 1 ' 9 6 $ 9 & 3 ( 1 $ 8 / 3 ' 8 / 3 ' & & & & 5 5 & & 5 5 5 5 3 - 3 - 5 5 5 5 5 5 & & 5 5 & & & & 3 - 3 - - 3 - 3 5 5 5 5 5 5 & 1 & 1 & & 5 5 5 5 & 1 & 1 3 - 3 - & & & & & & 5 5 , q , q , q , q 2 x w 2 x w 2 x w 2 x w ( 1 9 v h q v h 9 u h i 9 v h q v h 5 & 9 u h i 6 \ q f 9 & & 2 v f b 2 x w * 1 ' 1 & 1 & 8 / b v r 6 7 0 8 / b v r 6 7 0 & 1 & 1 & & 5 5 5 5 & & 5 5 & & 3 - 3 - 5 5 3 - 3 - demonstration boards AN2836 44/57 doc id 15084 rev 1 figure 46. eval6225pd component placement figure 47. eval6225pd top layer layout figure 48. eval6225pd bottom layer layout ! - v ! - v ! - v AN2836 demonstration boards doc id 15084 rev 1 45/57 a.3 eval6227pd a demonstration board has been produced to help the evaluation of the device in a powerso package. it implements a typical application with several added components. figure 50 shows the electrical schematic of the board. ta bl e 5 gives the part list. the demonstration board provides external connectors for the supply voltage, an external 5 v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external c board or the practispin tm tool. the practispin tm tool is composed of a graphic interface software running on a pc that connects with the hardware based on the st7 c, which contains upgradable firmware. this tool allows a fast and easy evaluation of the powerspin tm family of devices, allowing to drive dc, bldc and stepper motors, depending on the target device. the practispin tm connected to the eval6227pd can drive dc motors and inductive loads, allowing output voltage and current settings. table 5. eval6227pd part list part name value description cn1, cn2, cn3, cn4 2-pole connector cn5 34-pole connector c1 220 nf/100 v ceramic or polyester capacitor c2 220 nf/100 v ceramic or polyester capacitor c3 100 f/63 v capacitor c4 10 nf/100 v ceramic capacitor c5 10 f/16 v capacitor c6, c7 5.6 nf capacitor c8, c9 68 nf capacitor c10, c11 820 pf capacitor d1 bat46sw diode d3 bzx79c5v1 5.1 v zener diode jp1 3-pole jumper jp2, jp3, jp4, jp5, jp6 2-pole jumper r1 0 resistor r2 3.17 k 0.6 resistor r3, r4 100 k resistor r5, r16 20 k resistor r6, r7 100 k tr i m m e r r8, r17 2.2 k 0.4 resistor r9, r11, r12, r14 0.4 1 resistor r18, r15 5 k tr i m m e r u1 l6227pd l6227pd demonstration boards AN2836 46/57 doc id 15084 rev 1 the pc software also provides a power dissipa tion and thermal analysis section, intended to help give a fast evaluation of the device, package and dissipating copper area required by the user?s application, and to be a good starting point for designing an application (from the power dissipation and thermal point of view). running the demonstration board in standalone mode, instead, r15 and r18 set the reference voltage separately for the two bridge s, while r8, c8 and r17, c9 are low-pass filters which provide an external reference voltage by a pwm output of a c (see also the microstepping section in the an2839). using external v ref inputs, r5, r15, r16, r18 should be disconnected, unless the practispin st7 demonstration board is used. this board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see practispin tm documentation). r6, c10 and r7, c11 are used to set the off-time of the two channels of the ic. closing jp2 and jp3 is recommended for safe overcurrent protection. the 5 v voltage for logic inputs and for references (v refa and v refb ) is obtained from r2 and d3. depending on the supply voltage, the value of resistor r2 should be changed in order to ensure a correct biasing of d3. the jumper jp1 allows choosing the 5 v voltage from the internal zener diode network or pin 11 of cn5 (for example an external c board can provide 5 v to the demonstration board). also a cn2 connector can be used to provide an external 5 v voltage to the board (in that case r2, d3 should be disconnected). cn2, or pin 1 of cn5, can also be used to provide a 5v voltage to external circuits (as, for example, the practispin tm st7 board). in this case the current that can be drawn form the board depends on the supply voltage and on the value of r2. figure 51 to figure 53 show the placement of the components and the two-layer layout of the l6227pd demonstration board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device. figure 49. eval6227pd board ! - v * 0 2 * 0 2 * 0 2 AN2836 demonstration boards doc id 15084 rev 1 47/57 a.3.1 important notes jp1 : closed in int position for use with practispin tm st7 board r15, r18 : set the maximum current obtainable through practispin tm (see practispin tm documentation) r2 : recommended to be changed to adequate value (depending on supply voltage) to obtain 5 v across d3 jp2, jp3 : closed for safe overcurrent protection jp4, jp5: closed for use with practispin tm st7 board jp6: open for use with practispin tm st7 board demonstration boards AN2836 48/57 doc id 15084 rev 1 figure 50. eval6227pd electrical schematic ! - v ( 1 % ( 1 $ / , 0 , 7 b % / , 0 , 7 b $ , 1 , 1 , 1 , 1 , 1 , 1 9 5 ( ) $ , 1 / , 0 , 7 b $ , 1 ( 1 % / , 0 , 7 b % ( 1 $ 9 5 ( ) % / , 0 , 7 b % / , 0 , 7 b $ 9 5 ( ) b $ 9 5 ( ) b % 9 & & 5 ( ) 9 9 & & 5 ( ) 3 x o o 8 s 9 3 x o o 8 s 3 x o o 8 s / , 0 , 7 $ / , 0 , 7 % 9 5 ( ) $ 9 5 ( ) % 5 & $ 5 & % 6 ( 1 6 ( % 6 ( 1 6 ( $ 9 l q 2 & 0 3 % 3 7 2 8 7 % 3 7 2 8 7 $ 3 7 , 1 3 $ 2 3 , 1 7 , 1 7 2 & 0 3 $ 3 2 & 0 3 $ , & $ 3 $ 3 $ ' & b 5 ( ) 7 , 1 3 % 3 2 & 0 3 % , & $ 3 % 3 l q w h [ w & : & : & : & & & & & & & & & & & & & 1 & 1 & & 5 5 , 1 $ , 1 $ 6 ( 1 6 ( $ 5 & $ 2 8 7 $ * 1 ' * 1 ' 2 8 7 % 5 & % 6 ( 1 6 ( % , 1 % , 1 % 9 5 ( ) % ( 1 % 9 % 2 2 7 2 8 7 % 9 6 % * 1 ' * 1 ' 9 6 $ 2 8 7 $ 9 & 3 ( 1 $ 9 5 ( ) $ 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 8 / 3 ' 8 / 3 ' & & 5 5 3 - 3 - 5 5 & 1 & 1 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 & 1 & 1 & 1 & 1 5 5 5 5 3 - 3 - & 1 & 1 & & 5 5 3 - 3 - ' ' & & 5 5 3 - 3 - 5 5 ' ' 3 - 3 - & & - 3 - 3 AN2836 demonstration boards doc id 15084 rev 1 49/57 figure 51. eval6227pd component placement figure 52. eval6227pd top layer layout figure 53. eval6227pd bottom layer layout ! - v ! - v ! - v demonstration boards AN2836 50/57 doc id 15084 rev 1 a.4 eval6226qr a demonstration board has been produced to help the evaluation of the device in the qfn package. the board implemets a typical application that can be used as a reference design to drive a two-phase bipolar stepper motor up to 1 a dc, multiple dc motors and a wide range of inductive loads. thanks to the small footprint of l6226q (qfn 5x5 mm 32 leads), the pcb is very compact (27x24.5 mm). figure 58 shows the electrical schematic of the board. ta bl e 6 gives the part list. figure 54. eval6226qr the inx input pins drive the corresponding half bridge. when low logic level is applied, the low-side mosfet is switched on whereas a high logic level turns on the high-side mosfet. pins ena and enb are used to implement overcu rrent and thermal protection by connecting them respectively to the outputs diaga and diagb. table 6. eval6226qr part list part reference part value part description c1 220 nf/25 v capacitor c2 220 nf/63 v capacitor c3 10 nf/25 v capacitor c4 100 f/63 v capacitor c5, c6 5.6 nf capacitor d1 bat46sw diodes r1, r2, r3, r4 100 k 5% 0.25 w resistor r5, r6 10 k 1% 0.25 w resistor r9, r10 0.4 1 w resistor u1 l6226q dual full bridge in vfqfpn5x5 ! - v AN2836 demonstration boards doc id 15084 rev 1 51/57 the output current detection threshold is selectable by a resistor connected between the ic dedicated pins and ground. d1, c1 and c3 establish a charge pump circuit, which generates the supply voltage for the high-side integrated mosfets. due to voltage and current switching at relatively high frequency, these components are connected together through short paths in order to minimize induced noise on other circuitries. r1, r2 and c5, c6 are used by the overcurrent protection integrated circuitry (disable time t disable is about 200 s and delay time t delay about 1 s with the values in ta bl e 6 ). r5 and r6 are used to set the output current detection threshold at about 1.1 a typical value. figure 55 and 57 show the placement of the components and the two-layer layout of the eval6226qr reference design board. a gnd area has been used to improve the ic power dissipation. figure 55. eval6226qr component placement ! - v figure 56. eval6226qr top layer layout figure 57. eval6226qr bottom layer layout ! - v ! - v demonstration boards AN2836 52/57 doc id 15084 rev 1 figure 58. eval6226qr electrical schematic a.5 eval6227qr a demonstration board has been produced to help the evaluation of the device in a qfn package. the board implemets a typical application that can be used as a reference design to drive a two-phase bipolar stepper motor up to 1 a dc, multiple dc motors and a wide range of inductive loads. thanks to the small footprint of l6227q (qfn 5x5 mm 32 leads), the pcb is very compact (27x32 mm). figure 63 show the electrical schematic of the board. ta b l e 7 gives the part list. ! - v , 1 $ , 1 $ , 1 % , 1 % 2 8 7 $ 2 8 7 $ 2 8 7 % 2 8 7 % ( 1 $ ( 1 % ' , $ * $ ' , $ * % 9 6 6 * 1 ' 3 * 1 ' , 1 & & 5 5 5 5 ' % d w 6 : ' % d w 6 : & & & & 5 5 & & 5 5 & & & & 5 5 5 5 * 1 ' , 1 $ * 1 ' 6 ( 1 6 ( $ 9 % 2 2 7 , 1 $ 9 6 % 3 5 2 * & / $ , 1 % 9 6 $ 9 & 3 3 5 2 * & / % ( 1 % ( 1 $ , 1 % 2 & ' % 2 & ' $ 2 8 7 $ 6 ( 1 6 ( % 2 8 7 % 2 8 7 $ 2 8 7 % 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 8 / 9 ) 4 ) 3 1 [ 8 / 9 ) 4 ) 3 1 [ AN2836 demonstration boards doc id 15084 rev 1 53/57 figure 59. eval6226qr the inx input pins drive the corresponding half bridge. when low logic level is applied the low-side mosfet is switched on whereas a high logic level turns on the high-side mosfet. to perform the pwm current control an analog reference voltage should be provided to each channel of the driver. a fixed reference voltage can be easily obtained through a resistive divider from an external voltage rail and gnd (maybe the one supplying the c or the rest of the application). otherwise a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a c. table 7. eval6226qr part list part reference part value part description c1 220 nf/25 v capacitor c2 220 nf/63 v capacitor c3 10 nf/25 v capacitor c4 100 f/63 v capacitor c5, c6 5.6 nf capacitor c7, c10 820 pf capacitor c8, c9 220 nf capacitor d1 bat46sw diodes r1, r2, r3, r4, r7, r8, r9, r10 100 k 5% 0.25 w resistor r5, r6 10 k 1% 0.25 w resistor r11, r13 20 k 5% 0.25 w resistor r12, r14 2 k 1% 0.25 w resistor r20, r21 0.4 1 w resistor u1 l6227q dual full bridge in vfqfpn5x5 ! - v demonstration boards AN2836 54/57 doc id 15084 rev 1 d1, c1 and c3 establish a charge pump circuit, which generates the supply voltage for the high-side integrated mosfets. due to voltage and current switching at relatively high frequency, these components are connected together through short paths in order to minimize induced noise on other circuitries. r1, r2 and c5, c6 are used by the overcurrent protection integrated circuitry (disable time t disable is about 200 s and delay time t delay about 1 s with the values in ta bl e 7 ). r5, c7 and r6, c10 are used to set the off-time t off of the two pwm channels at about 50 s. the off-time should be adjusted according to the motor electrical characteristics and supply voltage, changing r5, c7 and r6, c10 values. r11, r12, c8 and r13, r14, c9 are low-pass filters which provide an external reference voltage through a pwm output of a c. figure 60 to 62 show the placement of the components and the two-layer layout of the eval6227qr reference design board. a gnd area has been used to improve the ic power dissipation. figure 60. eval6227qr component placement ! - v figure 61. eval6227qr top layer layout figure 62. eval6227qr bottom layer layout ! - v ! - v AN2836 demonstration boards doc id 15084 rev 1 55/57 figure 63. eval6227qr electrical schematic ! - v , 1 $ , 1 % , 1 % ( 1 $ ( 1 % ' , $ * $ ' , $ * % 9 6 6 * 1 ' 2 8 7 $ 2 8 7 $ 3 * 1 ' 2 8 7 % 2 8 7 % , 1 $ 5 ( ) $ 5 ( ) % 6 ( 1 6 ( $ 6 ( 1 6 ( % , 1 5 5 5 5 5 5 & & & & 5 5 5 5 * 1 ' , 1 $ * 1 ' 6 ( 1 6 ( $ 9 % 2 2 7 , 1 $ 9 6 % 5 & $ , 1 % 9 6 $ 9 & 3 5 & % ( 1 % ( 1 $ , 1 % 9 5 ( ) % 9 5 ( ) $ 2 8 7 $ 6 ( 1 6 ( % 2 8 7 % 2 8 7 $ 2 8 7 % 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 8 / 4 9 ) 4 ) 3 1 [ 8 / 4 9 ) 4 ) 3 1 [ 5 5 5 5 & & 5 5 & & & & 5 5 5 5 5 5 5 5 & & & & 5 5 & & ' ' 5 5 5 5 5 5 & & & & revision history AN2836 56/57 doc id 15084 rev 1 revision history table 8. document revision history date revision changes 22-jul-2009 1 initial release AN2836 doc id 15084 rev 1 57/57 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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